應屆畢業生
本科
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職位描述
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THE PERSON:
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
KEY RESPONSIBILITIES:
?Work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project
?technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc
PREFERRED EXPERIENCE:
?Master in Electrical Engineering, Computer Science or related
?Deep understanding on ASIC design verification flow
?RTL coding with Verilog/System Verilog
ACADEMIC CREDENTIALS:
MSEE with minimum of 6 years, or BSEE with minimum of 8 years experiences in digital ASIC/SOC design verification
注：聯系我時，請說是在蘿崗人才網上看到的。
工作地點
地址：上海浦東新區上海-浦東新區上海市浦東新區祖沖之路張江科技園
求職提示：用人單位發布虛假招聘信息，或以任何名義向求職者收取財物（如體檢費、置裝費、押金、服裝費、培訓費、身份證、畢業證等），均涉嫌違法，請求職者務必提高警惕。
職位發布者
HR
廣州思信電子科技有限公司
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電子技術·半導體·集成電路
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200-499人
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公司性質未知
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上海張江高科技園區祖沖之路2305號b幢610室
