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職責描述： 與設計架構師緊密合作，參與架構級別的討論。 IP級設計規范和RTL編碼 與綜合和物理設計團隊合作制定ASIC實施計劃。 與驗證工程師合作完成功能/性能測試計劃。 任職要求： 2年或3年以上ASIC/SoC設計經驗 較強的verilog開發實踐經驗 熟悉Perl、Makefile、 熟悉DSP, ARM, AXI優先考慮 熟悉內存控制器，有PCIE優先考慮。 較強的問題解決能力，團隊合作和溝通能力 Participate in architecture level discussion by closely working with design architects. IP level design spec and RTL coding Coworking with synthesis and physical design team on the ASIC implementation plan. Coworking with verification engineers on the function/performance test plan. 任職要求：MS with 2 years or BS with 3 years’ experience in ASIC/SoC design Strong hands-on verilog development experience Familiar with scripting languages like Perl, Makefile, … Familiar with DSP, ARM, AXI is a plus Knowledge on memory controller, PCIE is a big plus. Strong problem solving, teamwork and communication skills